Electronic Design

DDR Debug Toolkit provides test, debug, and analysis

Teledyne LeCroy has introduced the DDR Debug Toolkit for complete physical layer analysis of DDR 2/3/4 and LPDDR2/3 signals. Most oscilloscope-based DDR physical layer test tools on the market are ...
EDN

DDR Debug Toolkit for Entire DDR Design Cycle

Automatically separate Read and Write bursts with the DDR Debug Toolkit, eliminating the time consuming process of manual burst identification and simplifying the analysis of DDR system performance ...
The Providence Journal

DDR Debug Toolkit Provides Test, Debug and Analysis Tools for the Entire DDR Design Cycle

CHESTNUT RIDGE, N.Y., Nov. 24, 2014 /PRNewswire/ -- Teledyne LeCroy today introduces the DDR Debug Toolkit for complete physical layer analysis of DDR 2/3/4 and LPDDR2/3 signals. Most ...
Semiconductor Engineering

The PCB Engineer’s Guide To Successful DDR Bus Design

This paper tackles the critical signal integrity concerns encountered when designing, simulating, and analyzing DDR buses. The first section describes DDR bus design challenges that can be ...
Design-Reuse

New Lattice FPGA Design Tool Suite Includes Advanced Support for High Performance DDR Interfaces

HILLSBORO, OR, Nov 10, 2009-- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced Version 8.0 of its ispLEVER(R) FPGA design tool suite, which includes many enhancements for the design of ...
Semiconductor Engineering

When DDR DRAM Is Right For Automotive Systems

Most of the processors contained within automobiles are relatively small and with modest memory requirements that can be served by SRAM and non-volatile memory. The type of computing, image processing ...
EDN

DDR Debug Toolkit Provides Test, Debug and Analysis Tools for the Entire DDR Design Cycle

The ability to display up to ten eye diagrams simultaneously provides a high-level view of system performance during system bring-up. The multi-measurement scenario analysis capability easily lends ...